Field of the Invention
This invention relates to computing systems, and more particularly, to efficient management of operating modes within a semiconductor chip for optimal power and performance targets.
Description of the Relevant Art
The power consumption of modern integrated circuits (IC's) has become an increasing design issue with each generation of semiconductor chips. As power consumption increases, more costly cooling systems such as larger fans and heat sinks must be utilized in order to remove excess heat and prevent IC failure. However, cooling systems increase system costs. The IC power dissipation constraint is not only an issue for portable computers and mobile communication devices, but also for high-performance microprocessors, which may include multiple processor cores, or cores, and multiple pipelines within a core.
A power management unit (PMU) for an IC may disable portions of the IC when it detects or is otherwise informed that the portion is unused for a given period of time. Similarly, power-performance states (P-states) or dynamic voltage and frequency scaling (DVFS) techniques may be adjusted based on usage feedback of one or more processing units. These portions or processing units usually refer to general-purpose processors, graphics processors, and other processing units (although more gross or finer granularities are possible). Algorithms for the adjustments may assume worst-case thermal conditions. However, during typical usage and environment, the worst-case thermal conditions may not actually be met. Lower performance states and scaling may be selected during these times due to the assumptions in the algorithms. Therefore, available performance enhancements are not used. Changes to the algorithms may provide results that are not deterministic.
In view of the above, efficient methods and systems for efficient management of operating modes within an IC for optimal power and performance targets are desired.